24-hour online training – Time zone: CET

Dates

July 5th – 6th – 7th and 19th – 20th – 21st, 2021

Training duration

6 days, 4 hours per day

Course fees

For Part 1 & 2:

For Part 1, 2 & 3:

 

EARLY BIRD (till June 11th, 2021)

Benefit from 25% of discount on the course fees if you register  before June 11, 2021:

Registration deadline

The registration will be closed by June 28, 2021.

Number of seats

No more seats available for Part 3 but you can still register for Part 1 & 2. 

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Introduction

The main objective of the training is to provide the audience with the technical competence to design the digital control of power converters.
In this case, the medium-high power DC-DC converters have been used as a case study to show the digital control techniques. However the concepts can be used, directly, in other applications such as DC-AC inverters or AC-DC PFC.
In addition to the theoretical concepts on converter topologies, dynamic modeling and analysis of the specific effects of the digital loop, the course aims to be practical and allow the participant to “learn by doing”.
In the practical sessions, the participant must program in Code C the complete control loop from the scratch. In the additional practical sessions, the student will be able to program a digital HW board based on a System on Chip device (microprocessor + FPGA) and perform different experiments with which to assess the performance of the control developed.


What should you expect from the training?

This course is an introductory to advance-level course focused in the following specific objectives:


Audience description

This training course is recommended to everybody interested in the theoretical and practical design aspects of medium-high power converters and its control by means of digital control techniques. On the other hand, the course is eminently practical, therefore, the complete implementation of the control loop will be shown and experimentally verified.


Course structure

The Full Version Course is structured in the following blocks:

Part 1 Theoretical contents, simulation and design examples 3 days
Part 2 Online practice: design and simulation case studies 1 day
Part 3 Online practice: FPGA Programing and experimental test 2 days

 

Part 3 is opened only to participants who will have participated to Part 1 & 2 either at the reduced version course on March 8, 11, 15 and 18 or the full version course on July 5, 6, 7, 19 and 20.

Note: every day of the course, the session will be of 4 hours.


Price structure

When registering to the Full Version Course, you will be offered three options:

* (A 3% fee is applied for credit card payments). Payment will be due before the training.


Methodology

The focus is placed on Concepts

The explanations are focused on the concepts and physical meaning. Mathematical developments are also included as reference materials in annexes.

Tools

The methodology is summarized in Fig. 1. The steps are the following:

In these steps, the participant performs a “learn by doing” process. At the end of the training the participant has developed a complete digital control in a SoC.

Examples & Exercises

A large number of examples are used to show training explanations. A large number of “ready to use” C Code for the main loop blocks will be also provided (DPWM modulator, PID compensators, etc.) Exercises are proposed to be developed before the Practice Sessions. Then they will be resolved during the training.

Fig1-Control-Design-Programming-Flowchart-full-course

Fig. 1: Control Design & Programing Flowchart

 

Online hardware practices (part 3) will be developed using the Hardware Experimental Kit shown in Fig. 2. Power Smart Control S.L. (PSC) will provide each participant with a HW Experimental Kit that will be returned upon completion of the course. A deposit of 500€ will be asked.

Fig2-PSC-HW-Experimental-Kit

Fig. 2: PSC HW Experimental Kit

 

 

 


Instructor

Antonio-Lazaro Dr. Antonio Lázaro, Professor at Carlos III University of Madrid and Technical Director at Power Smart Control S.L. 
Antonio Lázaro was born in Madrid, Spain, in 1968. He received the M. Sc. in electrical engineering from the Universidad Politécnica de Madrid, Spain, in 1995. He received the Ph. D. in Electrical Engineering from the Universidad Carlos III de Madrid in 2003.
He has been an Assistant Professor of the Universidad Carlos III de Madrid since 1995. He has been involved in power electronics since 1994, participating in more than 80 research and development projects for industry. He holds 10 patents and software registrations and he has published nearly 140 papers in IEEE journals & conferences. His research interests are high-power DC-DC Converters, Power Factor Correction (PFC) Rectifiers, AC-DC inverters (railway and grid-connected applications), modeling and control of switching converters and digital control techniques.
Dr. Lazaro has originated and leaded the development of the Software SmartCtrl. He is the co-founder and technical director of Power Smart Control S.L. a spin-off company of Carlos III University of Madrid focused on the development of SmartCtrl and hardware high added-value control solutions for power electronics (SoC-FPGA control, HIL systems, real-time FPGA variable logging, automatic test-benches, etc.).

 


Language

English


Computer and temporary PSIM and SmartCtrl licenses

Each participant will have to bring a personal computer.

PSIM and SmartCtrl temporary licenses will be provided for the duration of the course.


Hardware Experimental KIT

Power Smart Control S.L. (PSC) will provide each participant with a HW Experimental Kit that will be returned upon completion of the course. A deposit will be asked..


Program:

Day 1- July 5, 2021 | ONLINE THEORETICAL SESSION

9 am – 11 am (2 hours) | Section I- Non-isolated and isolated topologies revision and steady-state analysis

  1. Multi-phase synschronous buck converter (MSB)
  2. Four switches buck-boost converter (4BB)
  3. Phase-shift full bridge (PSFB)
  4. Single-phase dual active bridge (DAB)
  5. Three-phase dual active bridge (3DAB)
  6. Series resonant converter
  7. LLC converter
  8. CLLC converter

11 am – 11.15 am: Coffee break

11.15 am – 13.15 pm (2 hours) | Section II- Dynamic modeling

  1. Steady-state and transient state
  2. Average models and small-signal model techniques
  3. Special transfer functions
    • Input impedance
    • Audio-susceptibility
    • Output impedance
  4. Feedforward compensations
    • Input coltage feedforward
    • Output voltage feedforward
    • Output current feedforward
  5. Analog control loop and digital control loop
  6. Options to represent the digital loop: SSS / SSZ / ZZZ
  7. Discretion of small-signal modles
  8. Discrete modeling techniques

 

Day 2 – July 6, 2021 | ONLINE THEORETICAL SESSION

9.30 am – 11 am (2 hours) | Section III: Modeling examples & control reference design

  1. Multi-phase synchronous buck converter (MSB)
  2. Phase-shift full bridge (PSFB)
    • Input series – Output parallel modular converters
    • Input parallel – Output series modular converters

11 am – 11.15 am: Coffee break

11.30 am – 1.15 pm (2 hours) | Section III: Modeling examples & control reference design

  1. Single-phase dual active bridge (DAB)
  2. LLC converter
  3. Four switches Buck-Boost converter

 

Day 3 – July 7, 2021 | ONLINE THEORETICAL SESSION

9 am – 11 am (2 hours) | Section IV: Digital PWM modulator and sampling techniques

  1. Modular block
    • Digital sawtooth carrier waveform
    • Digital triangular carier waveform
    • PWM Modulator
    • Resolution and gain of PWM modulator
    • Dead-times
  2. Analog voltage and current sensors
    • Hall effect current sensors
    • Single ended and differential analog amplifiers (transmitters and receptors)
    • Isolated voltage amplifiers
  3. Sampling techniques
    • Introduction
    • Sampling techniques of output voltage
    • Analog and digital filters
    • Sampling techniques of inductor current. Triangular and Sawtooth carrier waveforms
    • ADC Management: clock and SPI
    • ADC Resolution and ADC gain
    • Sensor and ADC gains rescaling looking for unity gain feedback

11 am – 11.15 am: Coffee break

11.15 am – 1.15 pm (2 hours) | Section V: Digital delay & Compensator Design and Implementation

  1. Digital delay
    • Physical concept
    • Transport delay and PWM delay
    • Effect on the loop transfer function
    • Single and double update
    • Multisampling techniques
    • Effect on feedforward compensations
  2. Sampling and modulating signal update scenarios
    • Single update and double update PWM
    • Multi-sampling techniques
    • Sampling techniques of inductor current. Triangular and Sawtooth carrier waveforms
    • Oversampling and moving average filter
  3. Digital compensators
    • Digital PI and PID
    • Transfer functions and difference equation
    • Anti-windup

 

Day 4 – July 19, 2021 | ONLINE PRACTICE – SIMULATION

Notes for on-line practice:

9.00 pm – 11.00 pm (2 hours) | Section VI: Simulation of a complete digital control loop

Exercise 1: PSIM C-block Implementation of a complete digital control for Boost Converter

Exercise 2: Basic Simulation in open loop to check the correct operation of the different blocks

Exercise 3: AC sweep simulation of loop transfer functions

Exercise 4: Design and implementation of PID compensator. using

    • Use Kp, Ti and Td as input parameters
    • Parallel implementation must be considered
    • Design the compensator to stabilize the transfer function G1(jω) x G2(jω), using SmartCtrl equation editor for the compensator block.PSIM C block implementation of PID compensator with anti-windup function

11 am – 11.15 am: Coffee break

11.15 am – 1.15 pm (2 hours) | Section VI: Simulation of a complete digital control loop

Exercise 5: PSIM simulation of the complete circuit under step changes on input voltage and load current

 

Additional exercises

Exercise 6: Developing a complete theoretical model using SmartCtrl Equation Editor for the following blocks:

Exercise 7: Limit Cycles. Reduce the resolution of the DWPM to be below the bits number of the ADC. Simulate the closed loop operation of the converter.

Day 5 – July 20, 2021 | ONLINE HARDWARE PRACTICE

Notes for on-line practice:

9.00 pm – 11.00 pm (2 hours) | Practice 1: Control Blocks Generation in Vivado

  1. Basic description of Vivado Design Suit
    • How to create a new project
    • Loading the Board files in the Zybo board
    • Basic code structure
    • General operation of an IP core
  2. HLS / VHDL blocks generation
    • DPWM modulator in VHDL / HLS
    • HLS PID compensator including anti windup and feed-forward compensations
    • VHDL ADC driver
  3. Synthetizing a new system in the SoC device
    • RTL exportation to Vivado
    • Project creation
    • Zynq configuration
    • Generation of the IP manager block
    • Exporting the hardware description to SDK

11 am – 11.15 am: Coffee break

11.15 am – 1.15 pm (2 hours) | Practice 2: AC Sweep Test in digital domain

  1. A first HW experiment 
    • Zybo board and power board connection
    • Basic Console to parameterize e.g. duty cycle
    • Testing the open loop operation
  2. Modulator structure
    • Duty cycle perturbation
    • Delays subtraction
  3. Measurement of the open loop gain Gvd
  4. Measurement of the open loop Gid 

Day 6 – July 21, 2021 | ONLINE PRACTICE

9.00 pm – 11.00 pm (2 hours) | Practice 3: Voltage Mode Test

  1. Synthesis of a new project including the current ADC driver
    • Generation of the current ADC driver block
    • Generation of the variable voltage reference block
  2. Basic Closed loop operation
    • Synthetizing a new project including the ADC driver
    • Testing the effect of PID constants
    • Testing the effect of the anti-windup

11 am – 11.15 am: Coffee break

11.15 am – 1.15 pm (2 hours) | Practice 4: Current Mode Test

  1. Synthesis of a new project including the current ADC driver
    • Generation of the current ADC driver block
    • Generation of the variable current reference block
  2. Tests
    • Basic closed loop test
    • Current reference variation

 

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General conditions for training:

Please register as early as possible if you plan to attend the training. As soon as the minimum of participants is reached, POWERSYS will confirm the course.
The registration to the course includes the lunches and coffee breaks. Participants will have to pay 100% in advance before the course.

Cancellation can be made according to POWERSYS’ General Conditions for courses:

Withdrawal from the Course:
In case you cannot attend the course after having registred, please contact us as soon as possible at marketing@powersys.fr
In case of cancellation three weeks OR MORE before the beginning of the course, the participants will not be charged.
In case of cancellation less than three weeks before the beginning of the course, POWERSYS will charge the participant 50% of the course fees.

Please note that POWERSYS will not reimburse any travel and/or accommodation expenditure in case of cancellation of the course. We recommend you to make your travel arrangements once the course is confirmed.

For French participants:

POWERSYS est enregistré en tant que prestataire de formation (auprès du Préfet de la Région Provence-Alpes-Côte d’Azur sous le numéro 93 13 13256 13). Une convention de formation peut être établie sur demande avant la date de formation.

Contact for any additional information:

Please feel free to contact us for any further information marketing@powersys.fr

 

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